A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches the technology, high turn-on/off capacitance ratio of LC-tank switched capacitors, addition to adjustable magnetic coupling technique, yields almost octave TR from 10.8 19.3GHz. A new method compensate tracking-bank resolution can maintain its quantization noise level over wide TR. scheme is adopted overcome metastability problem ADPLL operation. low-complexity TDC gain estimator reduces digital core progressive averaging time-division multiplexing. Among published PLLs with smaller than 0.1mm 2 , work achieves rms jitter 725fs internal mode ADPLL's phase detector (2.7-4.825GHz) yielding best overall figure-of-merit (FOM) -232dB. This topology features small (0.034mm ), (56.5%) good supply rejection (1.8%/V), resulting FOMs normalized (FOM T ) -247dB, xmlns:xlink="http://www.w3.org/1999/xlink">TA -262dB.